We've known for a while that AMD plans to offer verysophisticated DDR5 overclocking featureswith its next-gen Ryzen 7000-series 'Raphael' platform, but we still don't know all the details. However, now that the CPUs are weeks away, motherboards and their BIOSes are starting to float around the globe, revealing details about the new overclocking features. And they look quite impressive.The latest information comes fromYuri Bubliy, the developer of DRAM Calculator for Ryzen application, who, for obvious reasons, has access to BIOSes for some of the upcoming X670E motherboards.
According to Bubliy, AMD's next-gen platforms will reportedly feature unprecedented memory overclocking capabilities. In particular, BIOSes will offer two kinds of profiles for XMP/EXPO modules: high bandwidth and low latency. This probably refers to whether or not the modules run in coupled mode (1:1) with the memory controller and fabric, but only time will tell if that's the case. It also appears that the Infinity Fabric can be dialed up to 3 GHz, but it isn't clear if that will be attainable. The EXPO feature is much like XMP, so it will set in pre-assigned overclocking values to simplify speeding up your memory. Meanwhile, for those who do have time, AMD's upcoming platforms will let you set timings for each channel separately.
Indeed, AMD's Ryzen 7000-series platforms with the X670E chipset look to be an ultimate enthusiast platform, as it will allow owners to set asynchronous CPU and PCIe clocks, maximize CPU clocks for overclockers, and, perhaps more importantly, allows easy overclocking. The platform will also support CCX clock control (Zen 4 will feature four cores per CCX), making it possible to set clocks for the different CCXes independently. Furthermore, you will be able to control the host clock.
For those who want to go even further, AMD's Ryzen 7000-series systems will let you manually set the impendence for CPU ODT and DQ drive strengths as well as a variety of DRAM impendences to maximize memory overclocking further. Also, next-generation AMD platforms will allow manual adjustment of the CPU CK, CA, and CS drive strengths, again, to boost memory transfer rates.
This is certainly an unofficial source, and the information is preliminary, so you should take it with a grain of salt. However, AM5 motherboards are just weeks away, so we expect most of the aforementioned features to be available at launch.
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Anton Shilov
Freelance News Writer
Anton Shilov is a Freelance News Writer at Tom’s Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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3 CommentsComment from the forums
wifiburger omg can't believe this Zen4 is going back to Zen2 layout of 4ccx and no full L3 access to the cores
I'm very suspicious of IF hitting 3Ghz under 4ccx design since it's more power hungry , more links on the pcb
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InvalidError Impendence?
Must have meant impedance. Since actual impedance and a bunch of RX/TX characteristics are dictated by the specs with fine-tuning facilities during training, I'm not convinced of the benefits of letting users manually tweak those.
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-Fran- This is the first place I've read about Zen4 using 4cores per CCX, so back to two CCX'es per CCD, which would mean L3 is now only available to 4 cores at a time instead* of 8. I wonder if that change was due to the increase in L2 in order to compensate for latency? Hm... The other alternative is they're betting on VCache to increase the L3 for the CCX'es anyway, so they're not bothered by the split anymore? Interesting things you can read between the lines.
Anyway, making 4 cores per CCX does have the direct benefit of being able to power the groups with a bit more granularity, which can have positive effects in power consumption.
Other than that... I was expecting the IF to be clocked higher, but making it 3Ghz means it'll be able to run DDR5-6K 1:1, so maybe the sweet spot for Zen4 will be between DDR5-5200 and 6000? That is actually not bad at all.
I wish we could see a proper uArch diagram for it... I can't find any for Zen4 8(
Regards.
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